Very high speed signals must be distributed across an integrated circuit (IC) chip and, with advances in semiconductor technology, the variation in the total delay of a digital signal path is becoming a larger and larger problem in submicron technologies. One approach to addressing this variability is to employ current-mode logic (CML) circuits for high speed signal distribution. CML is a CMOS analog logic family that works by diverting current from one path to another, rather than by switching transistors on and off. CML is characterized by very fast operating speeds and high power dissipation. In order to achieve the speed requirements of today's IC designs, large CML circuits that operate at very high power may be utilized. Alternatively, a signal distribution path may include a mix of high-power signal distribution blocks, such as CML circuits, and low-power signal distribution blocks, such as digital complementary metal-oxide semiconductor (CMOS) circuits. Digital CMOS is a MOS logic family that uses both p-type and n-type material for the channels and is characterized by having lower power consumption per gate.
It is favorable to transmit high speed signals while expending very low power. Because the fabrication process is widely variable it may be possible to operate at a certain desired frequency using a string of low-power signal distribution blocks, such as digital CMOS circuits, in the signal distribution path that is located in a fast IC chip (i.e., fast due to certain fabrication process conditions that result in certain circuit characteristics). By contrast, a slow IC chip (i.e., slow due to different fabrication process conditions that result in different circuit characteristics), the low-power signal distribution blocks may not be capable of transmitting the signal at the desired frequency. Because circuit designers are required to design for a certain performance under the worst possible semiconductor process conditions, they may be required to design entirely with high-power signal distribution blocks, which is inefficient and wasteful in an IC chip that is capable of transmitting high speed signals with low-power signal distribution blocks.
A need exists for a flexible multimode logic element that is suitable for use in a configurable mixed-logic signal distribution path, in order to provide a digital signal path that is programmable to include combinations of high-power and/or low-power signal distribution blocks, while maintaining a certain desired performance level.